1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip inspection, and more particularly, to a test structure for resistive open detection using voltage contrast (VC) inspection, and a method of powering a test structure.
2. Background Art
In-line voltage contrast (VC) inspection is a powerful technique for detecting and isolating yield limiting defects in the semiconductor fabricating industry. In-line VC inspection includes scanning the wafer surface in which test structures exist with a scanning electron microscope (SEM). As the inspection proceeds, the SEM induces a charge on all electrically floating elements whereas any grounded elements remain at zero potential. This potential difference is visible to the SEM. In particular, for electron landing energies less than the second crossover of the secondary electron yield curve (approximately 1.5 keV for tungsten (W) and copper (Cu)), grounded elements appear bright whereas floating elements appear dark.
Test structures exploiting this phenomenon can be created for many yield limiting defects including metal, gate and active region shorts and opens, and via and contact opens. For example, FIGS. 1A-B, show a short (FIG. 1B) indicated by a normally floating (dark) element becoming bright, and an open (FIG. 1A) indicated when a normally bright element becomes dark. FIG. 1C shows a gate level open indicated when a normally bright element becomes dark. As shown, even if the defect causing the electrical failure is buried or extremely small, its existence is indicated by a change in the VC signal of the entire element. In addition, the exact location of an open is indicated by a change in the VC signal of the structure after the break.
In addition to timely detection of yield limiting defects, this technique has several other major advantages. First, the location of a defect is flagged by the VC signal. Even if the defect causing the short is buried or extremely small, the VC signal appears on the entire element. Second, large areas can be inspected providing a large volume of data.
In this area, resistive defects that are below the typical sensitivity of an inspection SEM present a challenge to detect. In particular, because of the nature of the voltage contrast effect, resistive defects such as opens of approximately 1 M-ohms or less cannot currently be detected. The maximum current generated by current inspection SEMs is around 500 nA. The percentage of this current that flows through the resistance is not enough to generate a voltage that is detectable above the noise level.
In some situations, resistive defects can be detected using VC inspection, but for reasons other than the VC effect. For instance, resistive contacts which are hollow may be detected because of the physical difference in the surface and the materials contrast if the liner is exposed. In many other situations, however, resistive defects exist without manifestation at the wafer surface during VC inspection. These include most resistive contacts and vias, and nickel silicide (NiSi) pipes. Currently, these types of defects with resistance below 1 M-ohms cannot be detected using VC inspection.